1. Field of the Invention
The present invention relates to an image processing apparatus, and in particular to a technique for sequentially inputting and processing image data during a predetermined time interval.
2. Description of the Related Art
As a signal processing apparatus capable of executing real-time video signal processing in parallel with processing for inputting an image into a processor, a configuration that provides an image signal bus synchronized with the image signal and a controller within the signal processing apparatus is known (for example, see Japanese Patent Laid-Open No. S60-138634).
However, although the configuration disclosed in Japanese Patent Laid-Open No. S60-138634 enables the parallel execution of image data transfer and CPU data processing, it is necessary to write the original data for the image processing performed by the CPU into a memory through the image signal bus at a predetermined timing. For this reason, with this system, it has been difficult to simultaneously perform processes whose timings of occurrence are not constant due to external factors, such as network processes, while also ensuring that the image processing is performed in real time.